With the development of semiconductor technology, higher driving current is required for faster transistors. Since the driving current of a transistor is proportional to the gate width of the transistor, in order to increase driving current, larger gate width is required. However, increase of the gate width conflicts with scaling of a semiconductor element. Thus, a novel three-dimensional structure transistor—fin field effect transistor (FinFET) is developed. In a FinFET structure, a gate is formed on a fin structure vertical to a substrate. By control of the gate, a conductive channel can be formed on both sides of the fin structure. The advantages of FinFETs include suppressing short channel effect (SCE), increasing driving current, and reducing leakage current.
Currently, FinFET still encounters many problems in manufacturing. The traditional process, as shown in FIG. 1(a) to FIG. 1(c), comprises: providing a substrate; removing part of the substrate to form a fin structure; and forming an insulation dielectric layer of an isolated fin structure. Generally, the step of forming an isolation dielectric layer comprises: depositing an insulation dielectric layer; performing chemical mechanical polishing (CMP) to stop at top of the fin structure; and etching part of the insulation dielectric layer so that the fin structure is exposed to a certain height. Since no etching barrier layer exists, the etching can only be stopped by controlling the etching time. Etching rates at different positions on a silicon chip may be different, and etching rates of different silicon chips may also be different. Thus, the fin exposed from the isolation dielectric layer may have different heights, which may affect the gate width of FinFETs, so that the device on different silicon chips and at different positions of silicon chips may have different properties, which is disadvantageous for large scale integration and mass production of devices.